1. Field of the Invention
This invention relates to a system and method for testing devices which conform to IEEE standard 1149.1-1990 or IEEE standard 1149.1-1990 (including IEEE standard 1149.1a-1993) or similar scan architecture in general and preferably but not limited to such testing of application specific integrated circuits (ASICs).
2. Brief Description of the Prior Art
IEEE standard 1149.1 (JTAG--Joint Test Action Group Standard) establishes a boundary scan implementation for ASIC interconnect testing. The JTAG standard is a scan-based architecture disposed on the ASIC under test as a part of the circuitry thereof having a scan input (receives serial data at an input pin) and a scan output (receives serial data from the ASIC at an output pin). The ASIC also includes a mode pin which indicates the desired operating mode at any point in time, a clock pin and a reset pin.
ASICs are tested both before and after they are assembled into packages (e.g. dual-in-line packages or DIPs, leadless chip carriers or LCCs, pin grid arrays, quad flat packs, etc.). Before assembly into a package, ASICs can be probed by special machines utilizing special probe cards and test vectors which consist of sets of input signals, output signals and bidirectional signals. These test vectors are used to provide information to the probe machine such that the ASIC can be electrically stimulated and verified. Each vector contains a set of input signals (stimulus) and a set of output signals which are verified by the probe machine after application of the input stimulus for each test vector.
Once the preassembled ASICs are verified to be functional, they are assembled into a packaged part and retested using the same type of apparatus, which is now equipped with a socket instead of a set of probes. The same set of test vectors is utilized to verify post assembly operation.
The JTAG standard is for use in verification of both the ASICs and board level interconnect after the ASICs have been mounted onto a circuit board. Because of the density of routing in use at present and because of the use of ASICs which do not use pins that are accessible while mounted on these circuit boards, it is becoming increasingly difficult to test circuit boards and the ASICs mounted thereon after assembly. The JTAG 1149.1 standard is a scheme including special circuitry which is built into the individual ASICs utilizing a boundary scan register located between the normal ASIC functioning circuitry and the pins of the ASICs. The special test features of the JTAG standard allow the JTAG circuitry on the ASICs to take over the interface of the ASICs and drive the output signals of the ASICs such that they can be captured by the JTAG boundary scan of the ASICs with which they are interconnected on the circuit board. The JTAG circuitry can also be used in a similar manner to test the internal operation of the ASICs while they are mounted on the circuit board. This is accomplished under the control of an external standard JTAG controller via a five sill serial interface consisting of a clock (TCK), test mode select (TMS), test data in (TDI), test data out (TDO) and the optional test reset signal (TRST.sub.--).
Initially, an instruction is scanned into the instruction shift register of the ASIC via the scan input. At the end of the scan, the instruction in the instruction shift register is immediately decoded (expanded via combinational logic such that all control signals are set to the appropriate state to perform the function defined by the instruction) and the decoded instructions or instruction decodes are stored in a set of parallel latches. These instruction decodes are used to control the actions of the test logic.
There are only three instructions required by the 1149.1 JTAG standard, but there is an unlimited number of optional instructions and each instruction has its own decode. Each decode is a combination of the control bits used to specify the actions of the test logic. In order to fully test the JTAG standard circuitry, each instruction must be shifted into the instruction shift register and measurements made to determine the state of each bit of the decode. Due to the difficulty in verifying the state of these decode bits based upon the response of the external pins of the ASIC, up to several thousand test vectors may be required for each bit of each instruction, resulting in huge vector counts, long test times and extra tester costs being incurred. Because each instruction must be fully tested and since each instruction test requires many test vectors, ASICs that use more than just a few JTAG instructions require an unacceptable number of test vectors. (The term "test vector" is a description of the state of the pins of an ASIC at any instant in time.) It is apparent that a great deal of tester time and expense can be saved by reducing the number of test vectors required to test the JTAG circuitry on the ASIC.
A problem that is addressed by the present invention is the testing of the JTAG circuit itself. Since the JTAG circuitry is contained within each ASIC, it at be verified before the ASIC can be certified as operational. In the prior art, this test was accomplished by shifting in a test instruction and observing what the chip did in response and the decode was checked by observation of the operation of the device after the instruction was sent. This testing is accomplished at probe and repeated after the ASIC is assembled as described above. Since the only way to verify proper operation of the ASIC is by monitoring the response of its output pins to a given input stimulus, testing of JTAG circuitry can be both complicated and time consuming. While IEEE standard 1149.1a-1990 only requires three specific instructions, it allows an infinite number of instructions to be used as defined by the ASIC designers and system engineers to ease system testing. These tests are conducted by scanning in a JTAG instruction and then manipulating the inputs of the ASIC while monitoring the outputs to verify that the proper response is achieved. Since each instruction is decoded into many bits (which are used to control the JTAG circuitry and are updated immediately after a new instruction is scanned in), and since each bit must be verified to be decoded properly for each instruction, many thousands of vectors may be required for complete verification. This results in long test times and the concomitant high test costs.